A semiconductor integrated circuit chip is typically fabricated with a back-end-of-line (BEOL) interconnect structure, which comprises multiple levels of metal lines and inter-level metal vias, to connect various integrated circuit components and devices that are fabricated as part of a front-end-of-line (FEOL) layer of the semiconductor integrated circuit chip. Current state of the art BEOL process technologies typically implement copper to form BEOL interconnects, as the use of copper material is known to significantly reduce resistance in the BEOL interconnect structure, resulting in improved conduction and higher performance. However, as copper interconnect structures are scaled down with smaller widths and pitches, copper interconnects are prone to void formation which takes place during copper filling of narrow trenches or openings formed in an interlevel dielectric (ILD) layer. The formation of voids in copper interconnects causes an increase in the electrical resistance of such interconnects, which in turn results in an increase of the RC delay of the integrated circuit.